Integrated circuits (“ICs”) use various sorts of devices (e.g., FETs, resistors, and diodes) to create logic and other types of circuits. The devices of an IC are connected to each other and to the terminals of the IC using patterned metal layers. As device dimensions shrink and ICs become more complex, wiring structures in ICs have become more challenging. In complex ICs, such as microprocessors, memory devices, and programmable logic devices, more than six patterned metals might be used in an IC.
Patterned metal layers are fabricated using any of several techniques, such as damascene, dual damascene, or patterned thin film techniques. Contacts and vias are used to connect one patterned metal layer to another, and to connect circuit elements in patterned metal layers to the semiconductor devices.
It is common in the art of IC processing to refer to the fabrication steps used in processing the semiconductors as front-end-of line (“FEOL”) processes, and to the fabrication steps used in processing the patterned metal layers and intervening layers of dielectric material(s) as back-end-of line (“BEOL”) processes.
“Inline” testing is done as a wafer or run of wafers is being processed, and inline techniques have been developed to evaluate both FEOL and BEOL processing. Inline testing and evaluation techniques provide a manufacturer with information regarding the quality of the wafers being fabricated, and whether the manufacturing processes are providing the desired results.
Basically, an optical or E-beam image of a portion of the IC or wafer is evaluated against a standard image or expected patterns. Differences between the test image and standard image are logged, and in some cases, used to adjust the process parameters of one or more fabrication steps. The inspection is typically repeated across the IC and for other ICs on the fabrication wafer.
Inline testing is important when fabricating devices with many patterned metal layers, because an electrical failure of the device could occur from a defect in any one of the patterned metal layers. A metal layer defect that causes an electrical failure is called a “killer defect”. A killer defect in a BEOL patterned metal layer often arises from particulate contamination (dust), but can arise from other sources, such as broken traces. Other types of defects might be observed during inline inspection, such as minor scratches, thick traces, thin traces, or uneven traces, or particulate contamination that does not cause a killer defect. Non-killer metal pattern defects provide desirable feedback to the fabrication line, which might use the information to adjust the parameters of a metal deposition, etch, or polish operation, for example. If defective patterned metal layers are being produced, it is desirable to detect and resolve the defects quickly to avoid yield loss.
However, an electrical failure in a finished or essentially finished IC might not be clearly associated with a defect identified in a metal pattern inspection. An overly sensitive inspection might capture differences between the images, or even noise, that do not cause an electrical failure.
Conventional techniques used to correlate metal pattern defects with electrical defects for complex ICs, such as FPGAs, rely on physical failure analysis (“PFA”), which is time consuming and typically occurs after the IC has been fabricated. Also, PFA might identify many apparent defects in a region of the IC, but the operator might not know which apparent defect caused the electrical failure.
In some instances, a bounding box associated with an electrical test vector is used to determine approximately where on the IC the killer defect occurred. This helps to focus the PFA on a smaller area. A test vector applied during electrical test is intended to produce an expected output. If the electrical test output is not the expected value, an area of the IC in which the killer defect is highly likely to have occurred (i.e., the bounding box) can be determined. The resultant bounding box depends on the test vector and type of IC being tested, and possibly on the result obtained from electrical test.
If the PFA can correctly identify the killer defect, parameters of the inline inspection process, such as sensitivity, pixel (defect) size, and filtering (defect shape), can be adjusted to improve correlation between the metal pattern defects and electrical failures. Unfortunately, even if the bounding box is relatively small, PFA is a time-consuming effort that often requires highly skilled technicians.
Techniques for correlating metal pattern defects captured during inline inspection with electrical failures that avoid the disadvantages of the prior art are desirable.